The four major process flows of wafer manufacturing

Historical Overview

20th Century Highlights

In , Carl Frosch and Lincoln Derick from Bell Laboratories unintentionally produced a silicon dioxide layer over a silicon wafer, observing surface passivation effects. By , they had developed methods for manufacturing silicon dioxide transistors, which were the pioneering planar field effect transistors with adjacent drain and source components. The significance of their findings rapidly gained recognition at Bell Labs, with memos circulated among senior staff prior to formal publication. At Shockley Semiconductor, the preprint had been shared with all senior staff, including Jean Hoerni, who later invented the planar process at Fairchild Semiconductor.

In , Bardeen patented an insulated-gate transistor (IGFET) featuring an inversion layer, a principle that serves as the foundation for present-day MOSFET technology. Enhanced MOSFET technology, known as CMOS, was formulated by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor, with commercial implementation by RCA in the late s for its -series integrated circuits—initially adopting a 20µm process and gradually scaling down to a 10µm process in subsequent years. Numerous early semiconductor manufacturers constructed their equipment for processes like ion implantation in-house.

By , Harold M. Manasevit documented the firsthand synthesis of silicon on sapphire while at North American Aviation's Autonetics division (now part of Boeing). His published findings alongside William Simpson appeared in the Journal of Applied Physics. In the following year, C.W. Mueller and P.H. Robinson successfully fashioned a MOSFET using the silicon-on-sapphire method at RCA Laboratories.

From the 1950s onwards, semiconductor manufacturing proliferated beyond the confines of Texas and California to encompass the global stage, extending into Asia, Europe, and the Middle East.

wafer dimensions have steadily escalated over the years, transitioning from 25mm in , then to 50mm in , 100mm in , 125mm in , 150mm in , and finally to a standard size of 200mm by .

As the industry advanced, manual handling of 2-inch wafers evolved; workers transitioned from utilizing tweezers to relying on vacuum wands to reduce contamination risks. The invention of wafer carriers or cassettes facilitated transporting multiple wafers while dipping them uniformly into wet etching and cleaning tanks. However, as wafer sizes increased to 100mm, maintaining uniform dipping quality posed challenges. By the time 150mm wafers were introduced, manual handling of these became perilous due to their weight, prompting the adoption of robotics for wafer handling processes.

In the 1990s, many corporations transitioned their semiconductor production technologies from bipolar to MOS technologies. Equipment costs in semiconductor manufacturing were notably high since this time.

In , KLA launched the inaugural automatic reticle and photomask inspection tool. In , they unveiled an automatic inspection tool for silicon wafers, superseding manual microscopic inspections.

In , SGS (currently STMicroelectronics) developed BCD, or BCDMOS—an innovative semiconductor manufacturing process utilizing bipolar, CMOS, and DMOS devices. Applied Materials also pioneered the first multi-chamber, cluster tool for wafer processing, namely the Precision .

Up until the 2000s, physical vapor deposition was the primary technique utilized for material deposition on wafers, until the emergence of chemical vapor deposition. Techniques involving diffusion pumps began to be phased out in favor of turbomolecular pumps, as the latter do not rely on oil—often a contaminant during vacuum processes.

The 200mm wafer debuted in and swiftly became the industry standard until 300mm wafers were launched in . Transition tools facilitated the transition from 150mm to both 200mm and 300mm applications. The semiconductor sector embraced larger wafers to accommodate the demand for more chips, as greater surface area per wafer became increasingly beneficial. The shift to 300mm wafers underscored the adoption of FOUPs, although various older technologies still produce goods on 200mm wafers like analog ICs, RF chips, power ICs, BCDMOS, and MEMS devices.

Specific processes, including cleaning, ion implantation, etching, annealing, and oxidation, transitioned towards single-wafer processing as opposed to batch processing for improved result reproducibility, a trend that similarly manifested in MEMS fabrication. In , Applied Materials launched the Producer, a cluster tool featuring chambers paired for wafer processing, which shared vacuum and supply lines while providing isolation, boosting productivity without compromising quality.

Moving into the 21st Century

The semiconductor industry today operates as a global entity, with leading manufacturers establishing facilities across the globe. Samsung Electronics claims the title of world's largest semiconductor manufacturer, having operations in South Korea and the USA. Intel ranks as the second-largest, with a global footprint stretching through Europe and Asia, as well as the USA. TSMC, the largest pure-play foundry, has a network across Taiwan, China, Singapore, and America. Meanwhile, fabless giants such as Qualcomm and Broadcom outsource production to firms like TSMC while maintaining facilities across various nations. With increasing semiconductor device utilization, durability became paramount, compelling manufacturers to design devices that endure over time, particularly noted as a challenge at the 10nm node.

Silicon-on-insulator (SOI) technology features prominently in AMD's processors fabricated on 130nm, 90nm, 65nm, 45nm and 32nm nodes since . During the 200mm to 300mm wafer transition, numerous bridge tools facilitated the dual capability to handle both wafer sizes, with as many as 18 firms capable of producing chips at the leading-edge 130nm process by .

By 2011, expectations were set for the adoption of 450mm wafers by 2015, with 675mm wafer production anticipated by .

Since , the nodal distinction has morphed into a commercial moniker, denoting emerging generations of processing technologies, lacking substantial relevance to gate length or interconnect spacing. For instance, the 7nm process by GlobalFoundries demonstrated similarities to Intel's 10nm process, leading to a blurring of conventional process node delineation; additionally, TSMC and Samsung's 10nm processes only offer modest transistor density improvement over Intel's 14nm process. Moreover, Intel has opted to rebrand its 10nm process as a 7nm variant.

As transistors scale downwards, novel design factors emerge, including self-heating issues and heightened visibility of electromigration since the 16nm node was reached.

Intel presented FinFET technology in (Fin-FETs surround the channel on three sides), enhancing energy efficiency and reducing gate delay—advancing performance significantly over planar devices in the 22nm node which suffered challenges associated with short-channel effects. A startup, SuVolta, pioneered the Deeply Depleted Channel (DDC) technology to rival FinFETs using lightly doped planar transistors at 65nm nodes.

By , numerous transistor architectures were being explored, meant to eventually succeed FinFET, mainly based around GAAFET concepts: various frameworks of horizontal and vertical nanowires, horizontal nanosheet transistors (like Samsung’s MBCFET and Intel's Nanoribbon), vertical FETs, and complementary FETs (CFET), along with several kinds of vertical TFETs and FinFETs utilizing III-V materials among others. FD-SOI emerged as a financially viable alternative to FinFETs.

As of now, major manufacturers including Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory, and Global Foundries mass produce chips using 14nm and 10nm processes. The 5nm processes were inaugurated by Samsung in , while the most densely populated node currently available is TSMC's 5nm N5 node, flaunting a staggering density of 171.3 million transistors per square millimeter. Announcements for 3nm node production were made by Samsung and TSMC in . GlobalFoundries, conversely, opted to cease the development of new nodes exceeding 12nm, deeming it financially unfeasible to establish a new fab for handling orders under 12nm technical specifications.

The period from 2020 to 2022 witnessed a global chip deficit. This scarcity, exacerbated by the ramifications of the COVID-19 pandemic, led numerous semiconductor companies to restrict their workforce's movements strictly within company grounds. In response, various nations provided financial aid to semiconductor firms to facilitate new fabs' construction. During this crisis, many companies fell victim to counterfeit chips. The crucial nature of semiconductors to the global economy and certain nations' national security is now openly recognized. For example, the US sought TSMC's non-manufacturing of semiconductors for Huawei, a Chinese entity.

Detailed Steps in Wafer Production Processes

This section outlines various techniques that are repeatedly applied throughout the construction of modern electronic devices; this enumeration does not denote a specific sequence nor does it imply that all methods are uniformly employed during manufacturing, as the actual order and methods used can vary based upon offerings by foundries or specific Integrated Device Manufacturers (IDMs) for their products. It is also conceivable that not all techniques are necessary for every semiconductor device. Equipment facilitating these processes is predominantly manufactured by a select group of companies. All machinery requires testing before operation in a semiconductor fabrication plant.

To further refine processing methods, techniques like Wright etching may be integrated.

To ensure product quality, a comparison between process nodes and various microscopic objects, alongside visible light wavelengths, demonstrates the progress of miniaturization.

Minimizing Contamination and Defects

In the past, when feature widths exceeded 10 micrometers, semiconductor purity was less critical than it is today. Workers during that time could operate in street clothing. However, as device integration surged, cleanroom protocols required advanced levels of cleanliness. Today, fabrication plants enforce strict air pressure with filtered air to expel even the tiniest particles that could settle on wafers and introduce defects. Cleanroom ceilings feature fan filter units (FFUs) positioned at regular intervals to ensure continual air replacement and filtration. Capital equipment used in semiconductor processing often includes in-built FFUs to enhance air quality in the equipment's EFEM, fostering improved contamination control.

Understanding Wafers

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A typical wafer consists of exceptionally pure silicon grown into mono-crystalline cylindrical ingots (boules) that attain diameters of up to 300 mm (approximately 12 inches) using the Czochralski method. These boules are then sliced into wafers around 0.75 mm thick and polished for a smooth and uniform surface. Throughout production, wafers are often grouped into lots represented by FOUPs, SMIFs, or wafer cassettes, serving as carriers. FOUPs and SMIFs can be autonomously moved within the fab between machinery by an automated OHT (Overhead Hoist Transport) in an Automated Material Handling System (AMHS). Additionally, wafer cassettes may be securely placed inside wafer boxes or carrying cases.

Core Processing Techniques

In semiconductor device fabrication, various processing stages are classified into four main categories: deposition, removal, patterning, and electrical property modification.

Contemporary modifications of electrical properties now extend to enhancing a material's dielectric constant in low-κ insulators via ultraviolet light exposure in UV processing (UVP). This modification regularly occurs through oxidation, forming semiconductor-insulator junctions like those evident in local oxidation of silicon (LOCOS), which is employed to construct metal oxide field-effect transistors. Presently, modern chips can possess up to eleven or more metallic levels, spanning over 300 sequential processing phases.

In semiconductor manufacturing, recipes define the conditions under which a wafer undergoes processing via specific machinery during the manufacturing process. Variability in processing remains a challenge, where wafers may not experience uniform processing or exhibit variances in quality or effectiveness across their surface.

Front-End Processing (FEOL)

Wafer processing divides into two stages: FEOL and BEOL. The FEOL stage concentrates on building transistors directly in silicon. The initial wafer is modified through epitaxial growth of a high-purity, defect-free silicon layer. In state-of-the-art logic devices, prior to silicon epitaxy, various tricks are deployed to enhance transistor performance. One strategy, the straining technique, introduces the deposition of silicon-germanium (SiGe). After epitaxiating silicon, the resulting stretched crystal lattice improves electronic mobility. Another method, known as silicon on insulator (SOI) technology, incorporates an insulator between the raw silicon wafer and the following silicon epitaxy layer, producing transistors with diminished parasitic traits. Equipment may consist of multiple chambers processing wafers through deposition and etching stages. Historically, wet benches with chemical solution tanks were utilized for cleaning and etching wafers.

When the technology arrived at the 90nm node, transistor channels employing strain engineering were introduced to enhance drive current in PMOS devices using regions featuring Silicon-Germanium, replicated similarly in NMOS devices at the 20nm node.

In , Intel debuted high-k/metal gate (HKMG) transistor technology at the 45nm node, supplanting previous polysilicon gates replaced by metal gates (prior aluminum gates) integrated during the late 1990s. High-k dielectrics such as hafnium oxide (HfO2) replaced silicon oxynitride (SiON) to impede excessive leakage current while permitting ongoing transistor scaling. However, HfO2 lacked compatibility with polysilicon gates, causing a requirement for a metal gate. Production utilized two primary methodologies: gate-first and gate-last techniques, each with distinct methodologies for integrating the high-k dielectric and gate materials. HKMG techniques extended from traditional planar transistors into FinFET and nanosheet transistor designs.

Since the advent of the 16nm/14nm node, Atomic Layer Etching (ALE) has increasingly found application; showcasing higher precision than traditional etching mechanisms. In realization, plasma ALE has become the standard, facilitating unidirectional material removal to cultivate structures with vertical walls, alongside thermal ALE that isotropically eliminates materials without vertical wall capability. Plasma ALE initially targeted contact etching for transistors but progressively integrated into structure formation since the 7nm node.

Gate Oxides and Implant Techniques

Front-end surface enhancements lead to gate dielectric (traditionally silicon dioxide) growth, gate patterning, source and drain regions shaping, alongside subsequent dopant implantation to achieve targeted electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors also form stacking configurations above the access transistor regions to ensure stability.

Back-End Processing (BEOL)

Metal Layer Integration

Following the crafting of various semiconductor devices, interconnections are developed to yield the targeted electrical circuits. This processes collectively fall under the BEOL (Back End of Line) phase (an aspect often confused with chip fabrication back-end, which encompasses packaging and testing phases). BEOL processing involves fashioning metallic interconnections insulated by dielectric layers. Traditionally, insulating materials came in SiO2 or silicate glass forms; however, novel low dielectric constant materials (low-κ dielectrics) are increasingly employed, achieving dielectric constants around 2.7 (as opposed to 3.82 for SiO2). Various materials with constants as low as 2.2 are now accessible for chip manufacturers.

BEOL techniques have been in use since the 350nm and 250nm nodes (0.35 and 0.25 micron nodes) alongside the onset of chemical-mechanical polishing. At that time, two metallic layers for interconnection, commonly referred to as metallization, were deemed standard practices.

Starting from the 22nm node, manufacturers began integrating middle-of-line (MOL) processes that interconnect transistors to the BEOL interconnect network. The MOL typically incorporates tungsten capabilities, presenting both upper and lower layers: the lower connects transistor junctions, while the upper addresses contacts with a tungsten plug linking transistors to the wider interconnect structures. Intel introduced contact-over-active-gate (COAG) at the 10nm node, optimizing contact placement directly over transistor gates to enhance transistor density.

Establishing Interconnection Paths

Traditionally, metal wires primarily utilized aluminum in a technique termed subtractive aluminum, involving blanket aluminum layers deposited, patterned, and then etched to produce isolated wires. Dielectric materials are then layered over the exposed wiring. Various metal layers interconnect via etching openings known as "vias" in insulating materials and depositing tungsten within, employing CVD techniques for tungsten hexafluoride utilization. This methodology remains prevalent, particularly in many memory chip applications, such as dynamic random-access memory (DRAM) that generally utilize a limited range of interconnect levels (typically totaling four).

In recent times, as the number of interconnect levels in logic increased due to extensive transistor networks in modern microprocessors, timing delays prompted a transition from aluminum to copper interconnect layers, alongside dielectric shifts from silicon dioxide to innovative low-κ insulators. This transition enhanced performance while reducing costs via damascene processing, effectively streamlining operations. With rising interconnect levels, planarization of preceding layers became crucial prior to further lithography; CMP (chemical-mechanical planarization) serves as the primary processing method to achieve this, although dry etch-back solutions are occasionally utilized when interconnects remain under three levels deep. Copper interconnect formations necessitate an electrically conductive barrier layer, often composed of tantalum nitride, to prevent copper diffusion into surrounding materials. In , IBM made pioneering moves in employing copper interconnect integrations.

Furthermore, in , Applied Materials proposed utilizing cobalt interconnections at the 22nm node, safeguarding copper through cobalt encapsulation within, rather than relying upon tantalum nitride thickness.

Wafer Metrology Advances

The highly systematic character of wafer processing demands stringent metrology across processing phases. For instance, thin film metrology leveraging techniques like ellipsometry and reflectometry plays a critical role in monitoring gate oxide thickness, along with refractive index and extinction coefficients for photoresist and other coatings. Wafer inspection tools confirm integrity of wafers after each process through final testing; excessive failures among dies necessitate complete wafer discarding to optimize costs associated with further processing outcomes.

Testing Semiconductor Devices

Upon completion of the front-end processing, semiconductor devices or chips need rigorous electrical evaluations to ascertain proper functionality. The resulting percentage of operational devices is construed as yield. Manufacturers often maintain confidentiality regarding yield data; values can drop as low as 30%, indicating only 30% of the chips on a wafer function as designed. Process variations contribute significantly to low yields, which testing helps preempt by avoiding the incorporation of defective chips into high-value packages.

Yield figures are not uniformly correlated with device (die or chip) sizes. For example, in December 2020, TSMC reported average yield figures of approximately 80%, with peak yield surpassing 90% for 5nm test chips sized 17.92 mm2. Yet, yield plummeted to 32% with die sizes scaling up to 100 mm2, reflective of defect density per unit area.

Electronic testers assess chips on wafers by applying tiny probes onto chip surfaces; they record failing chips with dye marks. Current methodologies allow for logging wafer test results in centralized databases such that chips can be sorted according to prescribed operational limits—maximum operating frequencies, etc. A graphical representation of this binned data yields wafer maps to trace defects and identify faulty chips. Bin sorting facilitates the reuse of potentially functional chips in lower-tier products, increasing overall device yield. Chips often feature testability enhancements such as scan chains or built-in self-tests to streamline testing and minimize costs. Furthermore, laser trimming may occur during testing of specific designs employing dedicated analog fabrication processes to achieve consistent resistance values as per design specs.

Well-engineered designs aim to statistically manage corners—extremes of silicon behavior resulting from the interplay of high operational temperatures and fabrication extremes, commonly addressing up to 64 corner scenarios.

Yielding Semiconductor Devices

Device yield, or die yield, indicates the proportion of operational chips or dies present on a wafer expressed as a percentage, reflecting variances in die counts contingent on chip size and wafer diameter. Yield degradation indicates losses in yield, historically attributed to dust particles, yet since the 1990s, main causes of degradation emerge from process variances, manufacturing methods, and machinery employed—though dust continues being problematic in older facilities. Dust particles increasingly impact yield as feature sizes shrink within contemporary processes. Automation and the incorporation of mini-environments throughout production have considerably mitigated dust-related defects. Ensuring high yield remains imperative for minimizing the market price of functional chips, and consequently, to mitigate production costs associated with wafer processing. Further yielding may also be influenced by both the chip design and fabrication practices.

Stringent containment and management of contaminants within the production cycle are essential to enhance yield metrics. Contaminants span chemical and dust particles; "killer defects" arise when critical defects originate from dust particles resulting in total device failure (like transistors). Various harmless defects exist in contrast. For instance, a particle size merely needs to measure 1/5 of the feature size to inflict a killer defect—thus if a feature measures 100nm, a consequent particle only requires 20nm dimensions to invoke failure conditions. Electrostatic charges may also adversely affect yields. Chemical contaminants encompassed heavy metals (iron, copper, etc.) along with alkali metals (sodium, potassium) that must be excluded from silicon contacts to avert adverse yield impacts. Various chemical baths help cleanse impurities from silicon surfaces; distinct mixtures yield varied effectiveness against different contaminants.

A range of models—Murphy's, Poisson's, binomial, Moore's, and Seeds'—serve to estimate yield variances. Notable conditions exist where no universal model applies; messages utilized depend on actual yield distribution across defective chips on the wafer. For instance, Murphy’s model presumes greater defect loss at wafer edges—non-functional chips are thus concentrated toward wafer perimeters, while Poisson’s model sees defects evenly dispersed throughout the wafer, and Seeds’ model assumes clustering of defective dies.

Shrinking die dimensions reduce production costs (due to increased counts per wafer), while contributing to higher yields owing to reduced defect probability, attributed to less surface area impacting the wafer volume. However, shrinking features necessitates tighter parameters for process variability and greater purity to uphold high yields during production. Metrology instruments inspect wafers during processing to predict yield; wafers suspected of defects may undergo scrapping to minimize processing costs.

Preparation of Dies

Upon completion of testing, a wafer typically undergoes thickness reduction through processes known as "backlap," "backfinish," or "wafer thinning," followed by scoring and ultimately breaking into standalone dies—popularly referred to as wafer dicing. Only properly functioning, unmarked chips progress toward packaging.

The Packaging Phase

Following die testing and sorting, the packaging phase commences. This involves securely mounting dies onto ceramic or plastic bases, connecting die/bond pads to package pins, and sealing the components. Historically, bond wires originally involved hand attachment during the early stages; Presently, machines fulfill this connection duty. Conventional wires typically comprised gold, consequently producing lead frames (pronounced "leed frame") of solder-coated copper; lead must be avoided as it poses toxicity concerns, making lead-free alternatives now mandatory under RoHS regulations. Typically, bond pads are positioned at die edges; however, modern Flip-chip packaging methodologies permit bond pads to disperse throughout a die's surface.

A chip scale package (CSP) typifies another innovative packaging strategy. A CSP, differing from a conventional plastic dual in-line package, is much closer in size to the die itself; CSPs can be devised for individual dies before they undergo dicing.

Subsequent to packaging, tested chips are reassessed to ascertain integrity—confirming that no damages occurred during the packaging stages and that the die-to-pin connections functioned precisely. A laser subsequently etches identification numbers and model designations onto the packaging surface. The sequences encompassing the die testing, packaging, then concluding with final evaluation of assembled chips are collectively known as the back end, or Assembly, Test, Marking and Packaging (ATMP) of semiconductor manufacturing, often conducted by OSAT (Outsourced Assembly and Test) entities distinct from semiconductor foundries, which focus on photolithography and etching as front-end operations.

Managing Hazardous Materials

The fabrication process engages various toxic substances, necessitating personnel protection from these dangerous agents. The high level of automation prevalent in integrated circuit fabrication significantly alleviates exposure risks. Most fabrication environments invest in sophisticated exhaust control mechanisms, including wet scrubbers, combustors, and heated absorber filters, to safeguard worker and environmental health.

Chronology of Commercial MOSFET Nodes

Related Topics

References

Additional Reading

• Kaeslin, Hubert (). Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication. Cambridge University Press.
• Wiki related to Chip Technology
• Yoshio, Nishi (). Handbook of Semiconductor Manufacturing Technology. CRC Press.

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